[Cryptography] RISC-V isn't the answer

Tom Mitchell mitch at niftyegg.com
Thu Jan 25 13:26:02 EST 2018


On Thu, Jan 25, 2018 at 2:46 AM, Peter Gutmann <pgut001 at cs.auckland.ac.nz>
wrote:

> Tony Arcieri <bascule at gmail.com> writes:
>
> >For an architecture like lowRISC (based on Berkeley's Rocket RISC-V core,
> I
> >believe), the answer is, for every word of memory (i.e. 64-bits) include a
> >set of attribute bits that control a number of rich attributes.
>
> How are you going to convince memory manufacturers to add the extra bits to
> their memory chips?  Or memory access controller designers to design custom
> controllers to deal with the extra bits?  Or customers to pay the same rate
> for 10% (or whatever) less usable RAM?
>

The market for ECC RAM is modest but shows how good a question this is.
For solving this problem a wider device even if part is unused can establish
a proof of concept.

Compared to data loss or penalties for data loss or breach early adopters
might just ignore the cost of unused bits and invest.
Memory chips are narrow and long or wide.   I believe building a memory
module is not a show stopper.   The chips to load the PWB are off the shelf.


-- 
  T o m    M i t c h e l l
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