[Cryptography] Does RISC V solve Spectre ?

[Raphael Jacquot]

On 03/21/2018 04:35 PM, tifkap wrote:
> Since Spectre and Meltdown are exploiting unintended consequences of 
> techniques (branch prediction, L1 & L2 cache in cpu, etc) that where
> developed (and even necessary ) for RISC familiy CPU's this seems like
> a really weird claim (google RISC vs. CISC ). 
> 
> It's possible to have CPU's using a RISC instuction set that are not 
> vulnerrable, but those CPU's would run on a really slow clock speed
> (so that memmory speed is not a bottleneck anymore) and would use 
> massive amounts of cores so that the total speed woud still be ok.
> 
> In short:
> 
> Instead of having a CPU with 4 cores at 2.0 Ghz each, a system like 
> that would have a CPU with 32 cores clocked at 500 Mhz.
> 

no,

RiscV is an ISA, for which there are a number of implementations possible..

Spectre and Meltdown are consequences of implementation fallacies /
bugs, most notably, allowing a process to access cached data whether or
not it is authorized to do so in certain circumstances.

those bugs have nothing to do with core frequency.

thus, RiscV may or may not be susceptible, depending on implementation
details.