[Cryptography] Does RISC V solve Spectre ?
tifkap
metzdowd at bikkel.org
Wed Mar 21 11:35:25 EDT 2018
Since Spectre and Meltdown are exploiting unintended consequences of
techniques (branch prediction, L1 & L2 cache in cpu, etc) that where
developed (and even necessary ) for RISC familiy CPU's this seems like
a really weird claim (google RISC vs. CISC ).
It's possible to have CPU's using a RISC instuction set that are not
vulnerrable, but those CPU's would run on a really slow clock speed
(so that memmory speed is not a bottleneck anymore) and would use
massive amounts of cores so that the total speed woud still be ok.
In short:
Instead of having a CPU with 4 cores at 2.0 Ghz each, a system like
that would have a CPU with 32 cores clocked at 500 Mhz.
> On 20 Mar 2018, at 11:52, Henry Baker <hbaker1 at pipeline.com> wrote:
>
> Someone has claimed to me that RISC V completely "solves" the Spectre
> problem.
> I'm still dubious. Perhaps it is a derivative/modification of RISC V ?
> Is there any in-depth analysis of RISC V & Spectre online somewhere?
>
> Eben Upton did a blog post on why it doesn't affect the RaspberryPI
>
> https://www.raspberrypi.org/blog/why-raspberry-pi-isnt-vulnerable-to
> -spectre-or-meltdown/
>
> f
>
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