[Cryptography] RISC-V branch predicting

[Ben Laurie]

On 7 February 2018 at 18:26, Tony Arcieri <bascule at gmail.com> wrote:

> On Mon, Feb 5, 2018 at 10:20 AM, Arnold Reinhold <agr at me.com> wrote:
>
>> Given that the RISC-V community has not gone very far in deploying
>> advanced risk prediction logic, maybe simple rubrics such as those
>> suggested in the first paragraph quoted above, along with improvements in
>> the software tool chain, such as maybe branch prediction pragmas and better
>> integrated profiling tools, could result in good performance while avoiding
>> Specte type problems.
>
>
> Branch prediction in and of itself is not a problem. The core problem
> underlying both Meltdown and Spectre is the CPU is speculating outside the
> current protection domain, because access control protections on memory are
> not enforced synchronously 100% of the time.
>
> I don't think anything fundamentally needs to change about how ISAs or
> speculation units are designed. What needs to change is how access control
> to memory is checked. Speculation units should proceed until they hit a
> memory access violation, at which point they should stop the current line
> of speculation, avoiding the problem of speculating outside the current
> protection domain strategically. The way to prevent a sidechannel is by
> closing it.
>
> In the RISC-V space, lowRISC has been doing a lot of research in the area
> of adding more metadata to memory which can be used for better access
> controls:
>
> http://www.lowrisc.org/
>

Speaking of research, we  have been looking at CHERI applied to RISC-V:
http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-907.pdf (chapter 6).

Speculative execution in a pure CHERI model automatically enforces bounds
that are the transitive closure of the bounds available to the current
process (that is, the current bounds in registers, plus all the bounds in
reachable memory).
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