[Cryptography] Secure erasure in C.

[Tom Mitchell]

On Tue, Sep 13, 2016 at 3:32 AM, Jerry Leichter <leichter at lrw.com> wrote:

> > On the hardware side I just learned that some ARM cores have a mix
> > of large and small cores that share memory and cache.  The information
> > leak and software reliability risk  is the little cores must always flush
> > cache as if they were a big core.
> > Code could migrate from one to another and the code would not
> > be able to know it moved or how wide the cache line is so it must
> > assume the largest possible.
> I'm not sure what the significance of two different core sizes is.

....

As Ard said the issue is the size of cache and cache lines.
His explanation is excellent..

The correct and optimum method differs for each size core.
Code that is correct for both is not optimum for both.

The instruction set allows the OS to move "code" from one to
the other and back in the manner of SMP.   However at the device  level,
cases like this discussion, getting it correct is important.  i.e. not
strictly
symmetric (equal).

In the SOC world such things are further complicated by functional blocks
for I/O subsystems (devices).   Since the cores appear symmetric but
are not this is one key for the device driver author and user space
memory mapped devices and drivers.
Then there are the GFX cores.   On the Raspberry Pi the boot loader
uses GPU hardware.

http://raspberrypi.stackexchange.com/questions/7122/level-of-hackability-of-raspberry-pi
"The most important thing you should know is that the RaspberryPi is a
strange beast where
the ARM CPU is the not main CPU - it's only a co-processor to the VideoCore
GPU."

And...
http://raspberrypi.stackexchange.com/questions/10489/how-does-raspberry-pi-boot

The R-Pi is only one example of the chaos of ARM and the IOT.







-- 
  T o m    M i t c h e l l
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