[Cryptography] Current state of tools for making parallelized bruteforcing easier on multiple FPGAs?

Ondrej Mikle ondrej.mikle at gmail.com
Fri Oct 18 17:06:07 EDT 2019


I remembered COPACOBANA and similar bruteforce-crackers that employed FPGAs.

Writing the code in VHDL/Verilog, synchronization and task distribution meant a
lot of work.

Does anyone know what the state is now?

Let's say I have few Spartan 6 LX150 with Cypress EZUSB interface lying around.

I tried writing parallelized and pipelined DES cracker some 6 years ago when
there were very few tools like migen and other abstractions from HDL languages,
fewer opensource place&route tools, etc. Took quite a while.

Can anyone estimate how much easier would it be to do the same task with newer
tools (like migen)?

On the top-level, it just means "put as many IP cores computing this function
there", then make connections that tell those cores the input ranges and wait if
any of them returns positively.

Of the most interest are easily-bruteforced ciphers, password hash attacks and
maybe some cracking where we know the key generation was biased due to bad RNG.

  O. Mikle

More information about the cryptography mailing list