[Cryptography] Does RISC V solve Spectre ?

tifkap metzdowd at bikkel.org
Sat Mar 24 10:24:08 EDT 2018


> On 03/21/2018 04:35 PM, tifkap wrote:
> > Since Spectre and Meltdown are exploiting unintended consequences of 
> > techniques (branch prediction, L1 & L2 cache in cpu, etc) that where
> > developed (and even necessary ) for RISC familiy CPU's this seems like
> > a really weird claim (google RISC vs. CISC ). 
> > 
> > It's possible to have CPU's using a RISC instuction set that are not 
> > vulnerrable, but those CPU's would run on a really slow clock speed
> > (so that memmory speed is not a bottleneck anymore) and would use 
> > massive amounts of cores so that the total speed woud still be ok.
> > 
> > In short:
> > 
> > Instead of having a CPU with 4 cores at 2.0 Ghz each, a system like 
> > that would have a CPU with 32 cores clocked at 500 Mhz.
> > 
> 
> no,
> 
> RiscV is an ISA, for which there are a number of implementations possible..
> 
> Spectre and Meltdown are consequences of implementation fallacies /
> bugs, most notably, allowing a process to access cached data whether or
> not it is authorized to do so in certain circumstances.

Yes, and why are OOE and Ln caches mimplemented?
 
> those bugs have nothing to do with core frequency.
 
They do. The techniques in question that are being exploited are specificly there
to a core with a high freqency is not waiting for memory all the time.

> thus, RiscV may or may not be susceptible, depending on implementation
> details.
 
Yes, a implementation that has no OOE and mem caches could run on a high frequency
but this would be totally useless (it would use more power, and would be waiting all
the time). 




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