[Cryptography] Power side channel mitigations
hbaker1 at pipeline.com
Wed Jun 6 19:08:14 EDT 2018
I've been reading up on power side-channels. As most people here should know, these attacks are completely devastating, and a large amount of HW/SW work has gone into mitigation.
However, most of the *hardware* work during the past 20 years seems to have focused on smartcards; very little hardware work (except for *algorithm* enhancements -- e.g., breaking up computations into Shamir secret-sharing) seems to have been done on general processors.
Yes, the smartcard HW ideas can be utilized for "TPM's" (Toilet Paper ModulesXXXXXXXXXXXXXXXXXXXXTrusted Platform Modules) and such, but these methods still leave the vast bulk of ordinary software programming & computation at risk.
Does anyone here know of any work at the hardware level for ordinary CPU's and GPU's ?
Thanks in advance for any links.
(BTW, please don't send me any links for specialized AES hardware; I've already accumulated perhaps 500 references for this kind of stuff -- I'm looking for ideas for protecting non-crypto-hardware & general purpose CPU's/GPU's.)
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