[Cryptography] RISC-V isn't the answer

[Bill Frantz]

On 1/22/18 at 7:45 AM, bascule at gmail.com (Tony Arcieri) wrote:

>lowRISC provides an every-word-tagged memory architecture. This information
>could be augmented to encode things like memory protection domains (or may
>already include the necessary information, I have not done an exhaustive
>survey of their tag bits), much in the same way KPTI is being leveraged as
>a page-level protection with the Linux's kernel's assistance. With
>information about the current protection domain encoded in every single
>word of memory, caches and memory controllers could physically deny access
>to words which are not tagged with the current protection domain. This
>would provide a central point of enforcement for *synchronous* checks which
>could prevent CPUs from speculating outside the current protection domain
>in the first place.

The immediate question that occurs to me is, "How do we handle 
shared memory? Both R/O and R/W?".

If we have a separate cache for each protection domain, then 
that domain is the only thing that can affect what is in that 
cache. Can we afford to fetch a shared word from a sister cache 
entry, or does that signal too much information? What about 
memory which is shared between mutually suspicious actors? 
(Probably R/O, but there may be uses for R/W.) There are a whole 
lot of questions.

One approach I like is a massive number of simple cores that 
don't speculate.

Cheers - Bill

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