5x speedup for AES using SSE5?

Sidney Markowitz sidney at sidney.com
Sat Aug 23 22:14:25 EDT 2008

Paul Crowley wrote, On 24/8/08 1:00 AM:
> http://www.ddj.com/hpc-high-performance-computing/201803067
> [...] However, glancing through the SSE5 specification, I 
> can't see at all how such a dramatic speedup might be achieved

A commenter on slashdot hinted at the vector permutation instructions, 
similar to those on Altivec, being useful:


Altivec is also known as VMX

That led me to this paper with a section on use of VMX vector operations 
in an AES implementation:


I didn't see performance comparisons or anything specific to SSE5, but 
it looks like the kind of thing that AMD might have meant.

  -- Sidney Markowitz

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