5x speedup for AES using SSE5?

[Sidney Markowitz]

Paul Crowley wrote, On 24/8/08 1:00 AM:
> http://www.ddj.com/hpc-high-performance-computing/201803067
> [...] However, glancing through the SSE5 specification, I 
> can't see at all how such a dramatic speedup might be achieved

A commenter on slashdot hinted at the vector permutation instructions, 
similar to those on Altivec, being useful:

http://developers.slashdot.org/comments.pl?sid=284695&cid=20423869

Altivec is also known as VMX
http://en.wikipedia.org/wiki/AltiVec

That led me to this paper with a section on use of VMX vector operations 
in an AES implementation:

http://diploma-thesis.siewior.net/html/diplomarbeitch3.html

I didn't see performance comparisons or anything specific to SSE5, but 
it looks like the kind of thing that AMD might have meant.

  -- Sidney Markowitz
     http://www.sidney.com

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