Re: AMDs new instructions for parallelism and support för side-channel attacks?

Joachim Strömbergson Joachim at Strombergson.com
Tue Aug 14 16:13:25 EDT 2007


Aloha!

Joachim Strömbergson skrev:
> Aloha!
> 
> I just saw om EE Times that AMD will start to extend their x86 CPUs with 
> instructions to support/help developers take advantage of the increasing 
> (potential) parallelism in their processors. First out are two 
> instructions that allows the developer to get info about instruction 
> completion as well as cache misses.
> 
> Considering the article by . about analysis of protection mechanism 
> against cache based timing attacks for AES [1] one could assume that 
> these instructions should be useful for writing side-channel resistant 
> implementations
> 
> But, do you think that the opppsite is also possible, that these 
> instructions might be a possible source for information leackage and 
> vector for side-channel attacks, at least local, inter process attacks? 
> I get a weird goodie-badie feeling when reading about these instructions...
> 
> 
> [1] Johannes Blömer and Volker Krummel. Analysis of countermeasures 
> against access driven cache attacks on AES
> http://eprint.iacr.org/2007/282.pdf

Just wanted to add a reference with info about the AMD announcement of 
their x86 extensions for parallelism:

http://www.eetimes.com/news/latest/showArticle.jhtml;jsessionid=TZEX4EJZT3L1CQSNDLSCKHA?articleID=201500201

-- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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