VIA Reveals Details of Next Generation C5J Esther Processor Core With Advanced Features For Securing E-Commerce Transactions
R. A. Hettinga
rah at shipwright.com
Wed May 19 11:49:26 EDT 2004
VIA Reveals Details of Next Generation C5J Esther Processor Core With
Advanced Features For Securing E-Commerce Transactions
Wednesday, May 19 2004 @ 09:05 AM
Contributed by: ByteEnable
San Jose, CA -- VIA Technologies, Inc, a leading innovator and developer of
silicon chip technologies and PC platform solutions, has revealed details
of the ultra power efficient VIA C5J "Esther" processor core manufactured
with IBM's advanced 90nm SOI process and optimized for information security
and e-commerce transactions.
With its ultra low power consumption, the VIA C5J Esther core targets
smart digital devices that extend the reach of x86 architecture further
into the consumer electronics, embedded and mobile fields than current
processor performance and thermal limitations allow. The new core is based
on IBM's advanced 90nm SOI manufacturing process, providing a significant
boost in processor speed within the same thermal bracket as current VIA
processors, and reducing maximum power consumption to a mere 3.5W at 1GHz.
Designed to be coupled with a range of feature rich chipsets from VIA, the
C5J Esther core will enable unprecedented performance of demanding
applications, such as high compression video streaming and data
encryption/decryption, from miniature, fanless devices.
The new C5J Esther core provides world-class security for e-commerce
transactions by accelerating RSA encryption and Secure Hashing (SHA-1 and
SHA-256), together with support for execution (NX) protection for
countering email worms/viruses. Other performance enhancing features
include a new faster Front Side Bus (FSB) of up to 800MHz, SSE2/SSE3
multimedia instructions, and a larger L2 cache.
"Our approach to processor design allows small, fanless devices to carry
out the most demanding security operations while simultaneously processing
today's increasingly sophisticated digital entertainment applications,"
said Glenn Henry, President, Centaur Technology. "The new architecture of
the C5J Esther core will allow us to ramp up processor speeds to 2GHz and
above within the same thermal design points as previous cores, opening up
new markets for our processors and extending the reach of the x86
architecture into new device categories."
More of the World's Most Advanced On-Die x86 Processor Security Features
The C5J Esther core extends the VIA PadLock Hardware Security Suite to
include execution (NX) protection, Montgomery Multiplier support for RSA
encryption and secure Hash (SHA-1 and SHA-256) algorithms in addition to
the VIA PadLock RNG and VIA PadLock ACE that are featured in the current
VIA C5P Nehemiah processor core. These hardware-based building blocks
effortlessly carry out operations within security programs and help to
improve overall system performance.
"It's great to see a CPU vendor provide hardware support for the most
important needs of crypto," said Phil Zimmermann, creator of PGP 1.0. "It's
always been hard to find a good entropy source for random number generation
on an unmanned server, a fast AES implementation for on-the-fly disk
encryption, and hardware support for fast public key operations for a
server to handle a high traffic workload from remote users. I wish all CPU
vendors would do this."
Execution (NX) protection prevents malicious code associated with worms or
viruses from executing and propagating from memory. The VIA C5J Esther
core's NX feature marks memory with an attribute that indicates that code
should not be executed from that memory, helping to prevent damage or
propagation of malicious code within x86 devices. Execution (NX) protection
is an important new hardware-based feature that will be supported in the
Microsoft® Windows® XP Service Pack 2.
The RSA algorithm is the most widely used public-key cryptography system
today and is increasingly important to e-commerce transactions that require
exchanging confidential information with websites or checking access
privileges. The major challenge facing public-key cryptography is that it
requires large amounts of processing power, posing a critical problem for
low power consumer electronics and embedded devices that cannot afford to
halt in the middle of a video stream or transaction while it does the heavy
lifting required by security programs. The VIA C5J Esther core features a
dedicated x86 instruction that performs Montgomery Multiplication, an
operation used to speed-up RSA cryptography, reducing the workload on the
processor and helping to improve overall system performance during
Secure Hash Algorithms are used in cryptography to provide digital
signatures that enable the recipient to verify the authenticity of the
origin of the message. The VIA C5P Esther core provides two Secure Hash
functions (SHA-1 and SHA-256) that assist in the creation and verification
of digital signatures through algorithms that are embedded in the processor
"The addition of hardware acceleration for SHA-1 hashing and large-integer
operations for public-key cryptography make VIA processors an excellent
choice for the implementation of security protocols such as IPsec, SSL/TLS,
and SSH, since they eliminate the often heavy CPU overhead normally imposed
by the crypto portions of these protocols," said Doctor Peter Gutmann of
the University of Auckland and author of "CryptLib". "This removes the need
to use the expensive external crypto-processors that are often required to
achieve acceptable performance under load."
"I am delighted to see that VIA's impressive on-chip AES capability is
being further extended to provide execution (NX) protection, SHA hashing
and support for public key cryptography using Montgomery Multiplication,"
said Dr. Brian Gladman, a leading information security specialist from
Worcester, United Kingdom. "This will put VIA processors in a leading
position for building secure applications offering high throughput and low
CPU security overheads."
More information, programmers guides and independent third party
evaluations of the VIA PadLock Hardware Security Suite are available from
the VIA PadLock Hardware Security Suite website.
IBM's 90nm SOI Process
The VIA C5J Esther core is being produced with IBM's groundbreaking
silicon manufacturing technologies that include copper interconnects,
silicon-on-insulator (SOI) and low-k dielectric insulation, together with
its advanced 90-nanometer (nm) process. These advanced manufacturing
technologies are designed to reduce power consumption and allow processor
speeds of 2GHz and beyond within the same thermal envelope as current VIA
IBM's 90nm manufacturing process provides greater scope for power saving
and performance enhancements by decreasing the internal distances traveled
by electronic signals within the processor. The low-k dielectric technique,
introduced by IBM, is a new method of building microchips that can deliver
boosts in computing speed and performance of up to a 30 percent by
facilitating the faster movement of electronic signals through the chip.
Similarly, IBM's SOI CMOS technology limits transistor leakage, further
increasing performance by an estimated 20-35% while reducing power
The C5J Esther processor core is designed by Centaur Technology, a wholly
owned subsidiary of VIA Technologies, Inc., and being manufactured by IBM
at their state-of-the-art 300mm (12 inch) foundry in East Fishkill, N.Y.
VIA at Embedded Processor Forum 2004
VIA is staging various live demonstrations of the VIA PadLock Hardware
Security Suite at the Embedded Processor Forum in the Empire Room on
Tuesday and Wednesday, 18th and 19th May, including a new AES encryption
benchmark tool that compares software-based encryption to hardware-based
encryption using the VIA Padlock ACE.
Also on display will be the soon to be released VIA EPIA SP12000 Mini-ITX
mainboard demonstrating high compression rate MPEG-4 and MPEG-2 digital
R. A. Hettinga <mailto: rah at ibuc.com>
The Internet Bearer Underwriting Corporation <http://www.ibuc.com/>
44 Farquhar Street, Boston, MA 02131 USA
"... however it may deserve respect for its usefulness and antiquity,
[predicting the end of the world] has not been found agreeable to
experience." -- Edward Gibbon, 'Decline and Fall of the Roman Empire'
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